PERIPH_CLK_SEL=PERIPH_CLK_SEL_0, IPG_PODF=IPG_PODF_0, AHB_PODF=AHB_PODF_0
CCM Bus Clock Divider Register
| IPG_PODF | Divider for ipg podf. 0 (IPG_PODF_0): divide by 1 1 (IPG_PODF_1): divide by 2 2 (IPG_PODF_2): divide by 3 3 (IPG_PODF_3): divide by 4 |
| AHB_PODF | Divider for AHB PODF 0 (AHB_PODF_0): divide by 1 1 (AHB_PODF_1): divide by 2 2 (AHB_PODF_2): divide by 3 3 (AHB_PODF_3): divide by 4 4 (AHB_PODF_4): divide by 5 5 (AHB_PODF_5): divide by 6 6 (AHB_PODF_6): divide by 7 7 (AHB_PODF_7): divide by 8 |
| PERIPH_CLK_SEL | Selector for peripheral main clock 0 (PERIPH_CLK_SEL_0): derive clock selected by CCM_CBCMR[CORE_CLK_PRE_SEL] 1 (PERIPH_CLK_SEL_1): derive clock selected by CCM_CBCMR[PERIPH_CLK2_SEL] |